welcome to this month's edition of MicroController Pros Corporation's Embedded News Digest, your source
for microcontroller and embedded system news.
This month's issue:
Analog Devices announced the next generation of TigerSHARC DSPs: the ADSP-TS201, ADSP-TS202, and ADSP-TS203. Shipping to customers today, the TigerSHARC devices delivering up to 1800 MFLOPS per Watt, 85 MFLOPS per dollar and 3600 MFLOPS per square inch. New members of the TigerSHARC family set new levels of fixed-point and floating-point signal processing performance by achieving 4.8 billion multiply accumulates per second (GMACS) and 3.6 billion floating-point operations per second (GFLOPS) at 600 MHz.
The ADSP-TS201’s balanced architecture achieves 5 Gbytes/second I/O bandwidth using new low voltage differential signal (LVDS) link port technology. The new TigerSHARC devices become the first to integrate 24 Mbits of embedded DRAM on a DSP. This large on-chip memory coupled with internal bandwidth of up to 38.4 Gbytes/second is essential to achieving higher performance.
The first low-cost offering in the TigerSHARC family, the ADSP-TS203 sells at less than $35.
Thumb-2 is a new blended instruction set combining both 16-bit and 32-bit instructions designed to deliver the best balance of density and performance, while at the same time retaining complete code compatibility with existing ARM solutions. Thumb-2 core technology uses 26 percent less memory than pure 32-bit code to reduce system cost, and at the same time, Thumb-2 core technology delivers 25 percent better performance than 16-bit code alone enabling designers to save power by reducing clock speed.
Intellectual property (IP) provider CAST, Inc. announced two new cores that are 100% software compatible with the popular M68HC05 and M68HC11 microcontroller families from Motorola. According to CAST, these cores provide better performance and features than the originals and have been silicon-proven in several ASIC designs.
Motorola introduced the first four members of its 1.8 volt low-power HCS08 family.
The first four 1.8 V devices in the HCS08 family are in production and
available today. Ten more HCS08 devices are planned for introduction later in
2003. Suggested resale pricing for the first four devices in 10,000-piece
The new H8S/2615F employs a 16-bit microcontroller H8S/2000 CPU core, and offers an operating frequency of 24 Hz-a 20% increase over current H8S/2612 Group products-and a minimum instruction execution time of 41.6 ns. The part features 64kB Flash, 4k RAM, CAN interface, six 16-bit multi-purpose timers, 16ch. 10-bit A/D converter and comes in a 80 pin QFP package. Sample price is 1300 Yen.
The new SH7641 incorporates a powerful SH3-DSP core offering CPU performance of 130 MIPS and DSP performance of 200 MOPS at a maximum operating frequency of 100 MHz. In addition, 144 Kbytes of single-cycle accessible SRAM plus 16 Kbytes of cache memory help speed up program processing time, for high-performance end-products.
The SH7641 features a wealth of on-chip peripheral functions, including a multifunction timer unit (MTU*2), a USB V2.0 Interface (Full Speed), and an I2C bus interface, enabling high-functionality products to be created. The external data bus can be connected directly to external memory, enabling system size and cost to be reduced. The chip comes in a 256 pin BGA package. Sample price is 2200 Yen.
The new SH7710 incorporates an IPsec accelerator, enabling communication processing to be executed at speeds upward of 20 Mbps while carrying out 3DES encryption processing. This enables the SH7710 to support secure broadband devices. In addition to 3DES, the IPsec accelerator also supports DES, MD5, and SHA-1 encryption.
The SH7710 has a SuperH RISC microprocessor SH3-DSP CPU core, operating at speeds up to 200 MHz and achieving a high processing capability of 260 MIPS. On-chip features include a 2 channel Ethernet controller, 2 syncronous serial interfaces, 2 UARTs and 3 timers. The device comes in a 256 pin HQFP package at a sample price of 3500 Yen.
Not a microcontroller, but an interesting peripheral for many microcontroller applications: The M45PE80 is an 8Mbit serial Flash offering fine granularity. Each page of 256 bytes can be individually erased and programmed. Furthermore a Write instruction offers the possibility to update data at the byte level. A page of 256 bytes can be written in 12ms, programmed in 2ms and erased in 10ms. The M45PExx is accessed through a standard SPI bus with an enhanced clock rate of 25MHz (!), for fast data transfer. It runs from a 2.7V to 3.6V supply and, to reduce power consumption, it features a deep power-down mode that draws just 1 microamp.
Texas Instruments announced the immediate availability of two low-cost DSP starter kits (DSKs), priced at US$395 each: the first low-cost DSK for the high-performance TMS320C64x fixed-point DSP family, and a new high-precision DSK for the TMS320C67x floating-point family.
Included on board the C6416 DSK is 16 MB of SDRAM. The TMS320C6416 fixed-point DSP at the heart of the C6416 DSK is a 600-megahertz (MHz) device that can achieve up to 4800 million instructions per second (MIPS) in performance. The processing-intensive C6416 DSP architecture features a two-level cache and Very-Long Instruction Word (VLIW) parallelism capable of performing eight 32-bit instructions per cycle.
The C6713 DSK includes 8MB of on-board SDRAM and an emulation header with a multichannel audio serial port (McASP), HPI and I2C interfaces. The C6713 DSK is based on the high-precision TMS320C6713 DSP, TI's most advanced floating-point DSP. With a two-level cache and VLIW architecture, the C6713 DSP achieves performance up to 1800 MIPS and 1350 million floating-point operations per second (MFLOPS). Other features common to both DSKs can be found at www.ti.com/c6000dsksp.
Toshiba announced two new versions of its TX49 family of MIPS-based RISC microprocessors. The new 64-bit MPUs, designated TMPR4955CFG-400 and TMPR4956CXBG-400, are fabricated with 90 nm CMOS process technology and are based on the TX49/H4 core. Power consumption is only 0.6 W when operating at their maximum frequency of 400 MHz; this is currently the lowest power consumption of any processor in this product category.
Incorporates a four-way set-associative, 32K-bytes instruction cache and
32K-bytes data cache. Integrates a floating point unit (FPU) that is separate
from the integer logic unit and realizes higher performance by making it
possible to perform integer operations and floating point operations
independently. Utilizes a 32-bit (TMPR4955CFG-400) or 64-bit (TMPR4956CXBG-400)
SysAD Bus with multiplexed address and data as a system interface in order to
interface with other SysAD-compatible devices. CPU core contains a dedicated
debugging support unit (DSU) and uses an external enhanced JTAG (EJTAG)
interface to perform execution control, such as setting breakpoints and
performing real-time analysis while running at the maximum operating frequency.
Samples of TMPR4955CFG-400 and TMPR4956CXBG-400 are scheduled to be available in August 2003. Sample pricing is estimated to be $35.00 per piece in 100-piece quantities for TMPR4955CFG-400 and $45.00 per piece for 100-piece quantities for TMPR4956CXBG-400. Mass production is slated for the end of 2003.
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