August 2006 Embedded News Digest

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Welcome to the August 2006 edition of MicroController Pros Corporation's Embedded News Digest, your source for microcontroller and embedded system news.

This month's issue:

Fujitsu Announces New Material for 256Mbit FeRAM using 65nm Technology
Microchip Opens Worldwide Network of 32 Regional Training Centers
Microchip Miniaturizes the Smallest PIC Microcontrollers
Microchip Introduces PIC18F4685 Family of CAN-enabled MCUs
NEC Announces New Line of CAN/LIN MCUs with Up to 1MB Flash
NEC Electronics Expands 8-Bit 78K0S/Kx1+ Flash MCU Family
NEC Unveils Innovative System-in-Package Technology

ZiLOG Offers Developer Studio II Software via Free Download

Fujitsu Announces New Material for 256Mbit FeRAM using 65nm Technology

Fujitsu Microelectronics America announced that the Tokyo Institute of Technology (Tokyo-Tech), Fujitsu Laboratories Ltd., and Fujitsu Limited have jointly developed a new material for a new generation of non-volatile Ferroelectric Random Access Memory (FeRAM). The material is a modified composition of Bismuth Ferrite (BiFeO3 or BFO), which enables data storage capacity up to five times greater than the materials currently used in FeRAM production.

New FeRAMs can be produced with Fujitsu's 65nm process technology using the BFO-based material in a device structure similar to the one used to build FeRAMs using 180nm technology. FeRAMs using this material can provide memory cell capacity up to 256Mbits.

The new FeRAMs will deliver the very low power consumption and high speeds required for new generations of personalized mobile electronic products such as IC cards, which must be small, easy to use, and provide very high security. The FeRAM technology is the most suitable non-volatile memory device for these kinds of devices and applications. Engineering sample shipments are planned for 2009.

BFO is a ferroelectric material composed of Bismuth, Iron and Oxygen atoms with a perovskite structure. Lead Zirconate Titanate (PZT or Pb(Zr,Ti)O3) is used as a ferroelectric material currently, but it has a lower-charge storage capability, so it also has limited scalability. The technology limits of PZT are expected to occur at the 130nm node, because as cell area decreases, higher polarization is required. This limit is expected to be reached in 2009.

An Mn-doped BFO thin-film capacitor was developed with the dual functions of decreasing leakage current and 180-220 µC/cm2 of switching charge, Qsw, which is equivalent to twice the remanent polarization, 2Pr. These results indicate significant scalability potential for future technology nodes.

FeRAMs built using 65nm technology can be produced using Mn-doped BFO, with the similar device structure of the FeRAM being produced using 180nm technology. FeRAMs using this new material will also provide significant scalability, enabling large memory capacity up to 2014.

Microchip Opens Worldwide Network of 32 Regional Training Centers

Microchip Technology announced a global network of Regional Training Centers (RTCs) to meet customer demands for more training more often. Engineers seeking to learn how to design with Microchip's development tools and silicon products now have access to 32 engineering labs in the Americas, Asia Pacific and Europe where they can attend hands-on workshops or seminars on a year-round basis.

These RTCs offer a multitude of courses -- covering a wide range of applications -- that provide expert instruction in a small classroom setting on new design methodologies, board-level "tips and tricks", and hands-on development tool projects that can make engineers more productive while increasing their own professional value.

Each RTC offers a wide range of course topics for skills levels from beginner to advanced. For additional information on RTC locations or to register for courses visit

Microchip Miniaturizes the Smallest PIC Microcontrollers

Microchip Technology announced that all members of its 6-pin PIC10F microcontroller family are now available in ultra-small 2 mm x 3 mm Dual Flat No-lead (DFN) packages for space-constrained applications. Additionally, three members of Microchip's 8-pin Baseline PIC microcontroller family are also available in a 2x3 DFN, providing additional I/O and functionality with the same footprint.

This 2x3 DFN packaging requires 30 percent less board space than the current SOT-23, and provides designers with a reduced height, which is often critical in handheld electronics. Key features of the 6-pin PIC10F200/202/204/206/220/222 and 8-pin PIC12F508/509/510 microcontrollers include: 8-bit analog-to-digital converter, comparator(s), internal oscillator operating at up to 8 MHz, 1.125 ms Device Reset Timer (DRT), 256 to 1K instructions (x12-bit program words) of Flash program memory, and 16 to 41 bytes of data RAM.

The PIC10F and Baseline PIC microcontroller families are supported by Microchip's development tools, including the free MPLAB Integrated Development Environment (IDE) software and all of Microchip's programmers.

In RoHS-compliant 2x3 DFN packages, the PIC10F and Baseline PIC microcontrollers are available now for general sampling. Volume production is available now for all six members of the PIC10F family, starting at $0.44 each in 10,000-unit quantities, while the Baseline PIC12F508/12F509/12F510 microcontrollers in 2x3 DFN are expected to be available for volume orders in the fourth quarter of 2006.

Microchip Introduces PIC18F4685 Family of CAN-enabled MCUs

Microchip Technology announced the four-member PIC18F4685 family of high-performance, low-power 8-bit CAN microcontrollers with 80 or 96 Kbytes of Flash and integrated EEPROM memory to accommodate the growing complexity of CAN applications. This is the largest amount of program memory available on any PIC18 microcontroller with an onboard ECAN module for CAN connectivity. Additionally, automotive and industrial designers can benefit from the small 28- and 44-pin package sizes of this family for space-constrained applications.

The PIC18F4685 offers enough code space for both the CAN protocol and advanced applications. And, each microcontroller in this family features Microchip's ECAN module, an easy-to-use scalable CAN 2.0B solution with the ability to switch between standard CAN operations and FIFO mode.

Key features of the PIC18F4685/4682/2685/2682 CAN microcontrollers include: 96 or 80 Kbytes of Flash program memory, 1 Kbyte of data EEPROM, 3.3 Kbytes of RAM, and a 10-bit ADC with 8 or 11 channels.

The PIC18F4685/4682/2685/2682 microcontrollers are available now for general sampling and volume-production ordering. The PIC18F4685/4682 come in 44-pin TQFP and 40-pin PDIP packages, and the PIC18F2685/2682 are available in 28-pin SOIC and PDIP packages, all of which are RoHS-compliant. Prices start at $5.26 each in 10,000-unit quantities.

NEC Announces New Line of CAN/LIN MCUs with Up to 1MB Flash

NEC Electronics America announced a new line of microcontrollers: the 8-bit Fx2 series and 32-bit Fx3 series, which are based on the company's 0.15-micron process technology and have embedded Flash memory optimized for automotive body and safety control applications.

Featuring pin counts ranging from 44 to 176, and Flash memory configurations ranging from 32KB to 1MB, the new line is composed of 29 MCUs: 13 based on the 8-bit 78K0 CPU core and 16 based on the 32-bit V850ES CPU core. All devices support CAN and LIN protocols. The products in both the 78K0/Fx2 and V850ES/Fx3 series are pin-compatible with NEC's previous-generation 78K0/Fx1+ and V850ES/Fx2 MCUs to provide current customers with a smooth migration path to the new series devices.

Samples of 78K0/Fx2 series MCUs are available now with volume production scheduled for October 2006. Samples of V850ES/Fx3 series MCUs are scheduled to be available in the coming months with volume production scheduled for December 2006.

NEC Electronics Expands 8-Bit 78K0S/Kx1+ Flash MCU Family

NEC Electronics announced the expansion of its 8-bit 78K0S/Kx1+ microcontroller series to include 10 new devices that provide seamless coverage of system requirements for multiple MCU applications. Three new 10-pin 78K0S/KU1+ MCUs are available in  a plastic shrink small-outline package (SSOP) that measures 4.4 by 3.72 mm. Flash memory capacities range from 1 to 4 KB.

The company is also adding to its existing low-pin-count series with seven new 78K0S/KB1+, 78K0S/KA1+ and 78K0S/KY1+ MCUs that are available with pin counts ranging from 16 to 30 and on-chip Flash memory ranging from 1 to 8 KB.

The 30-pin 78K0S/KB1+ MCUs feature 4 and 8 KB of Flash memory; the 20-pin 78K0S/KA1+ MCUs, 2 to 4 KB; and the 16-pin 78K0S/KY1+ MCUs, 1, 2 and 4 KB. The omission of an A/D converter in these seven devices allows designers to select only the functions they need, making these MCUs a cost-effective choice for applications in which analog data (such as temperature or weight data obtained from sensors) need not be converted into digital data by the MCU.

The 78K0S/KU1+ MCUs are in volume production now. Sample shipments of the 78K0S/KB1+, 78K0S/KA1+ and 78K0S/KY1+ devices are available now. Volume production for these MCUs is scheduled to begin in October 2006. Sample pricing is expected to range from US$1.30 to $2.

NEC Unveils Innovative System-in-Package Technology

NEC unveiled a new system-in-package (SiP) technology capable of stacking logic and gigabit-class memory in a single package to enable high-speed, high-definition image processing in mobile devices. The new SiP technology, SMAFTI (SMArt connection with Feed-Through Interposer), features a three-dimensional chip connection whose approximately 60-micron gap and 50-micron-pitch microbump between the logic and memory devices can support transmissions up to 100 gigabits per second (Gbps). Designers who use SMAFTI technology in cellular phones and other portable equipment that have stringent size and power constraints can achieve resolutions comparable to those achieved in high-definition television.

NEC developed the SMAFTI technology by leveraging three key enabling technologies: a 50-micron-pitch microbump interconnection technology, a 15-micron-thick feed-through interposer (FTI) based on superconnect technology, and a multichip assembly process.

The microbump interconnection technology makes it possible to realize low power dissipation, a small form factor, and high-speed interchip communication at more than 100 Gbps, ten times faster than conventional technologies. The small 50-micron-pitch interconnection size is the result of a silicon-to-silicon attachment process that effectively reduces the size of conventional pitch bumps and enables designers to accommodate four times the number of bumps in the same area. This process produces high-speed data transfers and is more reliable than the conventional silicon and organic substrate attachment process.

Superconnect technology is used in chip fabrication and has a copper signal trace 15 microns wide and a polyimide layer 7 microns thick -- half that of a conventional substrate. The 15-microns-thick FTI, which is based on superconnect technology, makes it possible to convert a chip's wiring pitch to 50 microns, and to fan out the pitch connection of an outer ball grid array to 500 microns. As a result, the routing of signals from a logic chip with a 50-micron pitch and memory connection points to universal substrate terminals can be simplified.

The multichip assembly process is an enhancement of existing wafer-based manufacturing processes that are typically used for SOC manufacturing. Memory chips are first mounted onto silicon wafers using wiring based on superconnect technology. Then the chips and wiring layer are molded by resin and the silicon wafer is removed. The BGA attachment process follows.

Products featuring SMAFTI technology are expected to be available during the first quarter of 2007 in a variety of lead-free package sizes. Availability is subject to change.

ZiLOG Offers Developer Studio II Software via Free Download

ZiLOG has made its ZiLOG Developer Studio II (ZDS II) software available free of charge via download from the Company's website.

ZDS II is a well-established Integrated Development Environment that provides a complete suite of software tools that support development with ZiLOG's eZ80Acclaim, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, and Crimzon product lines. Included in ZDS II are a Microsoft Windows-based project environment, editor, project manager, C compiler, assembler, linker, librarian, simulator, and debugger.

One major benefit of ZDS II is that it simplifies code development and helps bring products to market more rapidly. In addition, it is an extremely useful resource for writing 'code snippets' to test ideas or write functions. While many commercial customers are using ZDS II to develop production applications, it makes an ideal tool for embedded software development in an educational setting. Teachers and professors, for example, can use ZDS II as a tool for developing classes and workshops. Students can download the software to their home machines and/or laptops for class work or projects, while design engineers can evaluate the tools and silicon features without the expense of buying a C Compiler up front.

ZiLOG's software and tools are fully supported by their technical support desk. ZDS II can be downloaded at:

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