Microcontroller Interfaces, Part 3

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Asynchronous Interfaces Overview: UART and LIN Bus

By Volker Soffel

MicroController Pros Corporation

May 12, 2003

This article is part three in a series about various microcontroller communication interfaces. In part 1 and 2 of the series, I covered three of the most prevalent synchronous interfaces: SPI, Microwire and I2C. In part 3 it's time to take a closer look at asynchronous interfaces. I will start out with a general overview and then look in more detail at some UART based interfaces. In part 4 of this series we will  the CAN interface and the move on to Ethernet and USB.

Asynchronous Interfaces

While synchronous interfaces transmit and receive data in sync with a dedicated receive/transmit clock signal, asynchronous interfaces embed the clock information into the data stream. Therefore they are characterized by the absence of a dedicated receive/transmit clock signal. For devices to communicate in sync with each other, they need to agree on the same transmission speed (kbits/sec), the same protocol (number of data bits, stop bits, parity, etc), and they need to constantly re-sync to the clock embedded into the data stream. Re-syncing is usually achieved through start and stop bits (or frames) at defined positions in the data stream. To keep in synch, it is also required that the devices' system clock is stable within a few percent - simple R/C oscillators with +-25% tolerances or more will not work.

While synchronous interfaces were designed to allow for easy inter-device connections on the same printed circuit board, asynchronous interfaces were designed for connections via cables and to bridge larger distances. Distances can range from a few meters to up to a kilometer (with copper cable) depending on the interface. Applications range from simple point-to-point connections to complex bus networks with hundreds of devices in industrial control or automotive applications. Asynchronous interfaces vary greatly in key parameters that determine their suitability for a particular application, such as maximum bus length, maximum data transmission speed, multi-master capability, maximum number of devices on the bus, network topology, fail safety, data integrity and noise immunity.

The table below summarizes some key parameters for the most popular asynchronous interfaces.


Multi-Master Support

Typical Data Rates

Network Topology


Max. # of devices/ segment

Max. Cable Segment Length



10/100/1000 Mbps

Star (Hub or Switch)


2 (point-to-point)

100m (300'). Max 5 segments (4 repeaters): 500m (1500')



10 Mbps

Daisy Chain with terminating resistors

RG58 Coax


185m (555'). Max. 5 segments (4 repeaters): 925m (2775')

RS485 (UART based)


0.3 kbps 1 Mbps

Daisy Chain with terminating resistors


32 (2-wire bus), 64 (4-wire bus)

1330m (4000') @64kbps, much more with repeaters

RS422 (UART based)


0.3 kbps 1 Mbps

Daisy Chain with terminating resistors



1330m (4000')@64kbps, much more with repeaters

RS232C (UART based)


0.3 kbps 128 kbps


Various (ribbon, STP, UTP)


15m (45') @ 19.6 kbps, ~1.5m (4.5') @ 128 kbps

LIN      (UART based)


20 kbps

Daisy Chain

single wire


40m (120'), more with repeater



20 kbps 1 Mbps

Daisy Chain with terminating resistors



1000m (3000') @40kbps, 40m (120') @1Mbps, much more with repeaters



1.5/12/480 Mbps



2 (point-to-point), 127 per root host controller via USB hub

5m (15') Max. 7 segments (6 repeaters/hubs) 35m (105')


The OSI Layer Model

Before I continue covering asynchronous interface in more detail, let's take a short look at the OSI (Open Systems Interconnect) Layer Model, so that we have a common definition of terminology. The OSI layer model, developed by the ISO ((International Organization for Standardization), defines a framework for communications which has seven layers: 1-the physical layer, 2-the data link layer, 3-the network layer, 4-the transport layer, 5-the session layer, 6-the presentation layer, 7-the application layer. Control is passed from one layer to the next. A communication begins with the application layer on one end (for example, a sensor reading changes). The communication is passed through each of the seven layers down to the physical layer (which is the actual transmission of bits). Most interfaces that are integrated on microcontrollers only cover the data link layer, with the physical layer being implemented externally (with some exceptions). In some cases one and the same data link layer might be combined with different physical layer implementations to create different interface standards. In microcontroller applications layers 3 to 7 are typically implemented in software (with some hardware support).


The oldest and still most predominant asynchronous interface is the UART (Universal Asynchronous Receiver Transmitter). Some implementations support both a synchronous and asynchronous mode - then it is a USART (Universal Synchronous Asynchronous Receiver Transmitter). The same thing with just a different name is the Serial Communication Interface (SCI). With reference to the OSI model, a UART implements the data link layer (layer 2). The physical layer (layer1) is covered by several driver standards that all utilize the UART data link layer, among the most popular are RS232C, RS485 and RS422.

USARTs that are integrated on microcontrollers support data rates ranging from a few hundred bits per second (bps) up to 1.5Mbps. UART systems are typically either pure point-to-point connections of 2 devices (RS232C), or single master- multiple slave bus systems (RS422, RS485). It is possible to built multi-master RS422 and RS485 systems, but it requires the development of your own software protocol to handle bus arbitration (in case multiple masters want to send at the same time). Other interfaces, like CAN and Ethernet, handle bus arbitration in hardware and are therefore better suited for multi-master systems.

The basic UART data layer is very simple. A data packet consists of one start bit, 7,8 or 9 data bits, an optional parity bit (7 and 8 data bit modes only) and 1or 2 stop bits (as a curiosity some UARTs also support 7/8th for the last stop bit).

All the UART data link layer has to offer in terms of error checking is a simple (optional) parity bit. There is no acknowledgement from the receiving side, unless you implement some software protocol with acknowledgement or hardware handshaking mechanisms via standard microcontroller I/O pins. Better error checking also requires you to do it in software, which for CRC checksums can be pretty resource intensive.

The advantage of UART's simplicity is that it can be implemented in a relatively small silicon area and therefore commands a much smaller price premium than CAN, USB or Ethernet.  

The distances that can be bridged with a UART interface depend on the physical layer selected.

It is possible to connect two UART devices using the chips' CMOS logic signals. In that case a UART is not much different from the synchronous interfaces and only very short distances can be bridged (on the same board or within a closed system).

RS232C allows for cable connections from 1.5m  up to 20m, depending on the data rate selected, the quality of the cable and the output voltage swing of the RS232C transmitter (the RS232C spec provides much leeway on this).

RS485 and RS422 can bridge up to 1200m (4000'), again dependent on data rate, cable quality and physical layer driver/receiver characteristics (not all are created equal). To achieve such long distances and to increase noise immunity both RS422 and RS485 use differential data transmission.

LIN (Local Interconnect Network)

The newer LIN standard is a close cousin of the UART. LIN was specified by a consortium of automotive and semiconductor companies as a lower cost supplement to CAN with an emphasis on data integrity, error recovery and fail safety.  The LIN spec defines both physical layer (layer1) and data link layer (layer 2).

LIN is a single master multiple slave system. The "bus" is a single wire with reference to ground. The maximum bus length is therefore limited to 40m (120') with a maximum of 16 devices sharing the same bus.

LIN's data link layer provides improved control and error checking over a UART interface. It should be noted that all of LIN enhancements over a standard UART data link layer can be implemented in software, thus allowing you to do LIN with many of the standard integrated UART implementations found on microcontrollers - at the expense of quite some software and resource overhead.

Data is transmitted in fixed format message frames of selectable length. A message frame starts with a sync break signal, followed by synchronization and ID byte. Next follow 2, 4 or 8 data bytes and the CRC checksum byte. Sync break, Sync byte and ID Byte are always send by the master. The identifier describes the meaning of data. Slaves receive or transmit data based on the ID send by the master.

The Sync byte is used by the slave microcontrollers to automatically determine the bit rate and compensate for any clock tolerances. Through this trick it is possible to use high tolerance, cheap R/C or integrated oscillators for the slaves.

The LIN Bus specification 1.2 defines five different frames: data frame, sleep frame, wake-up frame, extended identifier frame and command identifier frame.

A LIN Master controller must be able to detect the following error conditions: bit error, identifier parity error; and, if expecting data from a slave, slave not responding error and checksum error. When receiving slaves must detect identifier parity errors and check sum errors; and bit errors when sending.

Some microcontroller manufacturers now integrate "enhanced" UARTs that provide some basic hardware support for specific LIN requirements, like, for example, generation of an interrupt upon receiving the synch break signal and automatic baud-rate calibration on every sync byte.

LIN's physical layer is basically a slew rate controlled NPN transistor whose collector is connected via a pull-up resistor and diode to the car battery plus terminal and whose emitter is connected to ground. The microcontroller's receive/transmit pin drives the basis of the transistor. The transistor has to be able to survive 40V across its collector-emitter connections and must be able to sink 200mA when switched on. This physical layer can of course be implemented externally to the microcontroller, but you can also find microcontrollers that have the physical interface integrated on-chip.

About the Author

Volker Soffel is the General Manager of MicroController Pros Corporation (uCPros). uCPros offers services in: Electronic system design with a focus on embedded systems; marketing and management consulting; employee training; technical writing and translations. uCPros also publishes a free monthly Embedded News Digest email newsletter, covering the latest events in the microcontroller industry. 

<< Part 2: SPI, Microwire and I2C Protocol Formats



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